The present invention relates in general to semiconductor devices and, more particularly, to integrated circuits that include a grid array package for housing a semiconductor die.
Integrated circuits that have high pin or lead counts often are housed in grid array packages to achieve a small size. For example, ball grid array (BGA) packages are used to provide chip scale or nearly chip scale integrated circuits that have between eighty and three hundred leads. A BGA package includes an interposer or substrate whose top surface has a region for mounting a semiconductor die. Wire bonds electrically connect nodes of the semiconductor die to bonding pads formed on the top surface. Throughholes or vias through the substrate are used for connecting the bonding pads to access pads formed on the bottom surface of the substrate. The access pads typically are arranged in a grid to minimize the area occupied by the integrated circuit's leads. A Bolder mask is patterned with openings over each access pad to accommodate small solder balls which are reflowed to function as leads of the BGA. package.
Current BGA packages suffer from a high cost due to the complex equipment needed to pick up the small solder balls, place them on the access pads and then to reflow the solder without disturbing the solder ball positions. This equipment is expensive and occupies a large area of a manufacturing facility. The cost is further increased because the access pads must be made large enough to ensure that the solder mask openings do not overlap the boundaries of the access pads, thereby reducing the number of routing channels between access pads and increasing the size of the substrate. A further problem is the presence of lead in the solder balls, which is considered to be an environmental and health hazard.
Hence, there is a need for an integrated circuit grid array package and method which reduces the size and manufacturing cost of the package as well as the risk of environmental and health damage.